-mem AddMux ALU Reg Read Reg Write 200ps 70ps 20ps 90ps 90ps 15ps 10ps 40ps 250ps PCSrc Add ALU Add result Shift left 2 Read ABLIS ALUSAtd operation register 1 Read Read MemWrite data 1 Memtol Zero register 2 instruction Registers Read data 2 ALU ALUAddress dataM Read Write register Write result Instruction memory tI data Write Data data memory Sign32 extend (a) What is the maximum achievable clock rate lor the datapath evabhle cloek ne ir the datapith above? Ignore the effects of th control tt Hinl Mark the vl timef iitd il b) What is the lateneya load asudtion n this datat (c) What is the laterex fore battion d) What is the liteuey af anAL (e) What is the CPlof this thsug? ata on saeh of the compenents in the figure above the pipelined catapathhowu noting the effects of the coutzol mit ad -mem AddMux ALU Reg Read Reg Write 200ps 70ps 20ps 90ps 90ps 15ps 10ps 40ps 250ps PCSrc Add ALU Add result Shift left 2 Read ABLIS ALUSAtd operation register 1 Read Read MemWrite data 1 Memtol Zero register 2 instruction Registers Read data 2 ALU ALUAddress dataM Read Write register Write result Instruction memory tI data Write Data data memory Sign32 extend (a) What is the maximum achievable clock rate lor the datapath evabhle cloek ne ir the datapith above? Ignore the effects of th control tt Hinl Mark the vl timef iitd il b) What is the lateneya load asudtion n this datat (c) What is the laterex fore battion d) What is the liteuey af anAL (e) What is the CPlof this thsug? ata on saeh of the compenents in the figure above the pipelined catapathhowu noting the effects of the coutzol mit ad