Memory Access Impact on Performance: Assume that main memory accesses take 80 ns and that memory accesses are 40% of all instructions. The L1 cache has a miss rate of 9% and a hit time of 0.58 ns.

1. Assume that the L1 hit time determines the cycle time for the processor. What is the clock rate?	1._______
2. What is the Average Memory Access Time for the processor (in ns)?	2.________
3. Use the AMAT from above to find the average number of cycles for a memory access. (CPI)	3. ________
4. Assuming a base CPI of 1.0 without any memory stalls (once the pipeline is loaded), what is the total average CPI for the processor?	4. _______

We will consider the addition of an L2 cache to try to reduce the average CPI; on a miss, P1 will now first check L2 cache, and only if that is a miss, will then need a main memory access. The L2 miss rate is 85%, and L2 hit time is 4.88ns

5.What is the AMAT for the processor, with the inclusion of the L2 cache? (in ns)	5._________
6. Using your answer for #5, what is the average CPI for a memory access for this processor including both L1 an L2 cache?	6. ________
7. Assuming a base CPI of 1.0 without any memory stalls, and using the same instruction mix as part 1question #6 of this question, what is the total CPI (for all instruction types) for P1 with the addition of L1 and L2 cache?	7._________