Memory latency (3 points - Correctness): A 5-stage pipelined processor has a base CPI of 1. Base CPI indicates CPI with no delay for misses. Load instructions are 32% of your program instructions. You have an I and D cache connected to memory with a 12 cycle miss penalty. Your I-cache has a 7% miss rate and your Dcache has 5% miss rate (Assume your program doesn't stall for store instructions). Assume all other instructions do not cause any delay. (a) What is the total CPI of the program? (b) What would be the total CPI of the program without caches? Memory latency (3 points - Correctness): A 5-stage pipelined processor has a base CPI of 1. Base CPI indicates CPI with no delay for misses. Load instructions are 32% of your program instructions. You have an I and D cache connected to memory with a 12 cycle miss penalty. Your I-cache has a 7% miss rate and your Dcache has 5% miss rate (Assume your program doesn't stall for store instructions). Assume all other instructions do not cause any delay. (a) What is the total CPI of the program? (b) What would be the total CPI of the program without caches