Minimization of circuits information is found in Rosen in Chapter 12. Assume a computer is being designed using only NAND gates. As we saw in class, a NOT gate has a single NAND gate with a splitter, an AND gate contains two NAND gates. There are three different possibilities for OR gates. 1) a + b takes three NAND gates 2) both a +5 and a+ b take two NAND gates 3) + b ab, so this case can be done with one NAND gate The simplification for ab+ ab takes four NAND gates, while ab+ ab takes five. Here are the LED versions of the digits from 0 to 9, and the versions of A, b, C d, E and F used in hexadecimal. HbLdEF -' 1_11_1 11_1_1 (6 points) Fill in the Karnaugh map below for the bottom horizontal LED for the decimal numbers, remembering to put DC in the boxes for values greater than 9. 84 84 84 Minimal circuit 21 21 21 21 Number of NAND gates