MIPS

1. (15 points) Below is a list of 32-bit memory address references, given as word addresses a. 1, 134, 212, 1, 135, 213, 162, 161,2, 44, 41,221 b. 6, 214, 175,214, 6, 84, 65, 174, 64, 105, 85,215 You are asked to optimize a cache design for the given references There are three direct-mapped cache designs possible, all with a total eight words of data: C1 has one-word blocks, C2 has two-words blocks, and C3 has four-word blocks. In terms of miss rate, which cache design is the best? If the miss stall time is 25 cycles, and C1 has an access time of 2 cycles, C2 takes 3 cycles, and C3 takes 5 cycles, which is the best cache design (in terms of stall time)