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MIPS Processor Design Problem 1: For Problem la and lb, we are running the program C19, with instruction mix: Loads Stores ALU Branches 35% 10%

MIPS Processor Design

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Problem 1: For Problem la and lb, we are running the program C19, with instruction mix: Loads Stores ALU Branches 35% 10% 35% 20% 70% of the loads incur load-use stalls; the number of cycles for each load-use stall depends on the version of the pipeline only. 65% of all branches are taken. Let the instruction count of C19 be IC. Problem la (20 points): Consider the 5-stage pipeline discussed in Chapter 4 up to Slide 73 or so. Taken branches take one stall, non-taken branches do not stall. Cycle time is 200 ps. What is the total execution time of C19 on this 5-stage pipeline? Make sure you show work and specify units clearly Problem 1b (25 points): Consider a new 8-stage MIPS pipeline, similar to the 7-stage pipeline discussed in Chapter 4 Slides 93-94, but with an extra stage: IF1 IF2 ID EX ME1 ME2 ME3 WB (Hence, data memory access takes 3 cycles, not 2. Everything else stays the same.) Cycle time is 120 ps. Refer to the discussion in class for the number of cycles for a load- use stall, and for the number of stalls taken by each type of branch. What is the total execution time of C19 on this 5-stage pipeline? Make sure you show work and specify units clearly. Problem 1: For Problem la and lb, we are running the program C19, with instruction mix: Loads Stores ALU Branches 35% 10% 35% 20% 70% of the loads incur load-use stalls; the number of cycles for each load-use stall depends on the version of the pipeline only. 65% of all branches are taken. Let the instruction count of C19 be IC. Problem la (20 points): Consider the 5-stage pipeline discussed in Chapter 4 up to Slide 73 or so. Taken branches take one stall, non-taken branches do not stall. Cycle time is 200 ps. What is the total execution time of C19 on this 5-stage pipeline? Make sure you show work and specify units clearly Problem 1b (25 points): Consider a new 8-stage MIPS pipeline, similar to the 7-stage pipeline discussed in Chapter 4 Slides 93-94, but with an extra stage: IF1 IF2 ID EX ME1 ME2 ME3 WB (Hence, data memory access takes 3 cycles, not 2. Everything else stays the same.) Cycle time is 120 ps. Refer to the discussion in class for the number of cycles for a load- use stall, and for the number of stalls taken by each type of branch. What is the total execution time of C19 on this 5-stage pipeline? Make sure you show work and specify units clearly

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