Modified Master slave latch. Please help. Thanks.

D Q CK Figure 1: A modified master-slave latch the initially latched value in the first latch of the pair is Q1 1 and it is Q20 The input is supposed to be stable during the second half of each clock cycle, and the outputs, too, will be recorded in the second half of the cloc cycles only. Will the output of the circuit remain stable during the entire clock cycle each time for every input, regardless of the initially latched values in Q1 and Q2? Explain. Do not count propagation delays. Starting from the given initial state Q 1, Q2-0, is there a non-empty sequence of inputs that will turn the output Q down to 0 in the end? Specify the sequence if it exists, or explain why it does not exist D Q CK Figure 1: A modified master-slave latch the initially latched value in the first latch of the pair is Q1 1 and it is Q20 The input is supposed to be stable during the second half of each clock cycle, and the outputs, too, will be recorded in the second half of the cloc cycles only. Will the output of the circuit remain stable during the entire clock cycle each time for every input, regardless of the initially latched values in Q1 and Q2? Explain. Do not count propagation delays. Starting from the given initial state Q 1, Q2-0, is there a non-empty sequence of inputs that will turn the output Q down to 0 in the end? Specify the sequence if it exists, or explain why it does not exist