Modify the single cycle datapath to add the support for the following instruction.

Instruction: SEQ Rd,Rs,Rt

Interpretation: Reg[Rd] = Boolean value (0 or 1) of (Reg[Rs] == Reg[Rs])

i.e. a modification of SLT instruction, but it will set RD when RS=RT

Identify Existing blocks used, and suggest new blocks if required. Also suggest if any new control signal is needed.

DRAW ON THE DIAGRAM BELOW. YOU CAN DO IT USING ANY SOFTWARE TO DRAW (MSPAINT etc), or you can use your own page and insert a pic below the diagram for answer.

Branch M u 3x 4 Add M Add u ALU operation Data Mem Write Address PC Register # Registers Register # Address Instruction ALU M Zero Instruction memory 3x Data memory Register # RegWrite Data MemRead Control