Module $2.$ Pipeline Enhancement

In this project, you are provided with an architecture presented in a PowerPoint file format $($m$2\_$pipeline.pptx$),$ similar to those discussed in the lecture slides. However, upon careful examination, it becomes evident that the given architecture lacks support for certain instructions within the MIPS instruction set.$$ Your task is to enhance the given architecture to support the operation of specific MIPS instructions by integrating additional wires, multiplexers, or control signals. When adding wires from the instruction memory, please specify the bit numbers where applicable. When adding multiplexers, make sure to include selection signals as well as the inputs. Alongside the enhancements, you will also be required to provide explanations for the modifications and briefly answer a few questions regarding the given instructions.

$1.$

$2.$You are required to submit two files:$$Diagram of your enhanced architecture $($m$2\_$pipeline.pdf or m$2\_$pipeline.pptx$)$:$$You have the option to either hand draw the modifications and submit a scanned$$copy as a PDF file or revise the PowerPoint $($pptx$)$ file directly. Regardless of the$$method chosen, your modifications should be clearly visible.$$Explanation and answers $($m$2\_$answers.txt$)$:$$This file should include the outlining of your modifications along with the rationale$$behind each of them. It should also contain answers to the questions related to the$$given instructions.

$1)$ The current architecture is unable to execute the jr instruction. Please make appropriate modifications to the architecture to enable the operation and answer the following questions.

instruction format: jr RS sample instruction: jr $$4$

OPCODE RS RT RD SHAMT FUNCT $00000000100000000000000000001000$

Q$1-1)$ Why is the jr instruction not classified as a J$-$type instruction?

Q$1-2)$ What rationale could explain why the jr instruction is not categorized as an I$-$type instruction?

$2)$ The current architecture is unable to execute the sll $($Shift Left Logical$)$ instruction. Please make appropriate modifications to the architecture to enable the operation and answer the following questions. You may assume that the ALU takes two operands, source register and shift amount, to perform the shift operation.

instruction format: sll RD$,$ RT$,$ SHAMT sample instruction: sll $$8,$ $$9,5$

OPCODE RS RT RD SHAMT FUNCT $00000000000010010100000101000000$

Q$2-1)$ What factors might explain the choice of $rt over $rs as the source register for the sll instruction?

Q$2-2)$ What could be some reasons why shift operations utilize shamt as the operand instead of using two source registers?