module ALU(

input logic [3:0] aluin_a,input logic [3:0] aluin_b, input logic [3:0] opcode, input Cin, output logic [3:0] alu_out, output logic Cout, output logic OF, output logic zero); // Declare any internal logic signals here //your code. Tip : Please try to indent your code in a proper manner. You will save lot of time while debugging if anything doesnt work the way it should // endmodule 2. Inside the top-level, you may choose to instantiate a 4-bit adder which in turn instantiates 1- bit adder modules. Inputs to the 4-bit adder can be chosen based on OPCODES using a case statement so that you can do shifting. You may also choose to just do an addition operation yourself here and let the compiler / SystemVerilog choose the best adder for you. 3. 4-bit subtraction can be implemented by taking the 2s compliment of aluin_b prior to presenting it as an input to the adder module if you choose to use your own adder module Opcode specifications: Specifications for the ALU: The VERILOG model you implement should be for a 4-bit arithmetic/logic unit (ALU) which has as inputs two 4-bit vectors aluin_a and aluin_b as well as a carry in, Cin. The output is a 4-bit vector alu_out.

write the Verilog code for a 4-bit arithmetic/logic unit (ALU)?

The ALU will be 4bits wide.

List of Input signals: aluin_a 4 bits : 4 bit primary input 1

aluin_b 4 bits : 4 bit primary input 2

opcode 4 bits : 4 bit input to specify operand on primary inputs 1 and 2

Cin 1 bit : 1 bit input for Carry-in

List of Output signals:

alu_out 4 bits : 4 bit primary output

Cout 1 bit : 1 bit output for Carry Out

OF 1 bit : 1 bit flag to denote Over Flow in alu_out

zero 1bit : 1 bit flag to denote zero result in alu_out

1.a 4-bit adder which in turn instantiates 1- bit adder modules. Inputs to the 4-bit adder can be chosen based on OPCODES using a case statement so that you can do shifting.

2.4-bit subtraction can be implemented by taking the 2s compliment of aluin_b prior to presenting it as an input to the adder module.

Opcode specifications: OPCODE Operatiorn alu out=aluin a aluin b alu-out = aluin a + aluin, b + Cin alu out-aluin a-aluin b C3C2C1CO|Description 0111 Add 0110 add with Cin 0101 sub b from a 0100 logical shift right alu_out- aluin_a logical shift right by aluin b 0011 arith shift right 0010 logical shift left 0001 arith shift left 0000 bit wise inversion lalu out= NOT alu in a alu out=aluin a arith shift right by aluin b alu out=aluin a logical shift left by a luin b alu-out = aluina arith shift left by aluin, b Specifications for the ALU: The VERILOG model you implement should be for a 4-bit arithmetic/logic unit (ALU) which has as inputs two 4-bit vectors aluin a and aluin b as well as a carry in, Cin. The output is a 4-bit vector alu_out. The ALU should operate on the inputs depending on the control inputs C in the Opcode specifications: OPCODE Operatiorn alu out=aluin a aluin b alu-out = aluin a + aluin, b + Cin alu out-aluin a-aluin b C3C2C1CO|Description 0111 Add 0110 add with Cin 0101 sub b from a 0100 logical shift right alu_out- aluin_a logical shift right by aluin b 0011 arith shift right 0010 logical shift left 0001 arith shift left 0000 bit wise inversion lalu out= NOT alu in a alu out=aluin a arith shift right by aluin b alu out=aluin a logical shift left by a luin b alu-out = aluina arith shift left by aluin, b Specifications for the ALU: The VERILOG model you implement should be for a 4-bit arithmetic/logic unit (ALU) which has as inputs two 4-bit vectors aluin a and aluin b as well as a carry in, Cin. The output is a 4-bit vector alu_out. The ALU should operate on the inputs depending on the control inputs C in the