module dff (clk, reset, d, q, qb); //write required parts here reg q; //write required parts here always @(posedge clk or posedge reset) begin if (reset) begin q <= 1'b1; end else begin q <= d; end end endmodule

module test; //write required parts here dff DFF(.clk(clk), .reset(reset), .d(d), .q(q), .qb(qb)); initial begin $dumpfile("dump.vcd"); $dumpvars(1); $display("Reset flop."); clk = 0; reset = 1; d = 1'bx; display; $display("Release reset."); d = 1; reset = 0; display; $display("Toggle clk."); clk = 1; display; end task display; #1 $display("d:%0h, q:%0h, qb:%0h", d, q, qb); endtask endmodule