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module DU _ 2 ( clk , rst , a , b , c , d , e , sel 1 , sel 2 ,

module DU_2(clk, rst, a, b, c, d, e, sel1, sel2, sel3, sel4, self, sel6, selml,
input [15:0]a,b,c,d,e;
input clk,rst,1d1,1d2,1d3,1d4;
input [1:0] se11;
input sel2, se13, sel4, sel5, sel6, selm1, selm2;
output [1.5:0] R1, R2, R3, R4, mul_out, add_out;
reg[1-3:0]-R1,R2,R3,R4, mul_out, add_out:
reg 15:0 sr1,sr2,sr3,sr4,srbar(5),sr6,sm1,sm2;
// Max 1
alwayse (sel1, mul_out, add_out, a)
gcase (sel1)
2*630:sx1=a;
2*501 : sx1= add_out;
defaule: sr1=4 thes?
endicase
alwayse (sel2, c, add out)
if (seliz)
sr2=add _out:
else
sr2=c;
18 misk
alwayse (se13, b, add out)
if (sel3)
s.3= add out :
else
s3=b :
//mux 4
always0(se-14, en dy
f(sen4)
elise
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