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module Main ( out _ 0 , CLK , inp _ 0 , reset, present _ 0 2 3 ) ; output [ 1 5
module Mainout CLK inp reset, present;
output : out;
input inp reset, present CLK;
wire andout, Q Q Q Q Q Q Q Q Q Q Q xorout, Q Q xorout, Q xorout, Q Q ;
wire : Splittercmb;
assign andout inp & CLK;
DflipFlop Q andout, xorout, reset present;
assign Splittercmb Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q ;
assign out Splittercmb;
DflipFlop Q andout, Q reset present;
DflipFlop Q andout, Q reset present;
DflipFlop Q andout, Q reset present;
DflipFlop Q andout, Q reset present;
DflipFlop Q andout, Q reset present;
DflipFlop Q andout, Q reset present;
DflipFlop Q andout, Q reset present;
DflipFlop Q andout, Q reset present;
DflipFlop Q andout, Q reset present;
DflipFlop Q andout, Q reset present;
assign xorout Q xorout;
DflipFlop Q andout, Q reset present;
DflipFlop Q andout, Q reset present;
assign xorout Q xorout;
DflipFlop Q andout, Q reset present;
assign xorout Q Q ;
DflipFlop Q andout, Q reset present;
DflipFlop Q andout, Q reset present;
endmodule
module DflipFlopq qinv, clk d arst pre, en;
parameter WIDTH ;
output reg WIDTH: q qinv;
input clk arst pre, en;
input WIDTH: d;
always @ posedge clk or posedge arst
if arst begin
q b;
qinv b;
end else if en ;
else begin
q d;
qinv ~d;
end
endmodule
timescale nsps
module TestBench;
reg inp reset, present CLK;
wire : out;
Main DUTout CLK inp reset, present;
always begin
# CLK ~CLK; Toggle clock every time units
end
initial begin
CLK ;
inp;
reset ; Assert reset initially
present;
# reset ; Deassert reset after time units
# present; Assert present for time units
# present; Deassert present
Apply input data
# inp; Set inp to to provide input data
# inp;
# inp;
# inp;
# $finish; Terminate simulation after time units
end
initial begin
$dumpfiletestbenchvcd;
$dumpvars TestBench;
end
always @posedge CLK begin
$displayoutb h out out;
end
endmodule
Separate out the design file and the testbench file so you can simulate the circuit using
the EDA playground.
c You will need to edit the testbench and write code to toggle the reset and preset and
enable the clock.
d You will need to edit the design file so that the DD flipflop works the same as it does in
CircuitVerse code to use the preset signal must be integrated into the reset if
statement
e Run a simulation to generate numbers
f Hand in your list of numbers in both binary and hexadecimal format.
g Hand in a timing diagram of your simulation
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