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Multi - Cycle Arch. Given the following code. Assume that x and y are arrays of words and the base address of x is stored

Multi-Cycle Arch. Given the following code. Assume that x and y are arrays of words and the base address of x is stored in R1 and the base address of y is stored in R2. Assume that each add operation takes 3 cycles to execute, each lw operation 4 cycles, each store sw takes 3 cycles, and each branch (bne) instruction takes 2 cycles to execute. The T represents Temp registers. All numbers are in decimal.
add T0, zero, zero # T0= i =0+0=0
add T1, R1, zero # T1= address of x[i]+0
add T2, R2, zero # T2= address of y[i]+0
add T3, zero, 101
Loop: lw T4,0(T2) # Load T4 with M[T2+0] value
add T5, T4, C # C is a constant value
sw T5,0(T1) # Store T5 to M[T1+0]
add T0, T0,1
add T1, T1,4
add T2, T2,4
142: bne T0, T3,-7 # Loops if branch is taken
144: add T0, T0,200
What is the PC value for the SW instruction?
Multiple choice 1 Question 2
120
128
124
134
Calculate the branch target address?
Multiple choice 2 Question 2
130
-7
116
133
What happens after T0 becomes equal to T3?
Multiple choice 3 Question 2
T0 increases by 100
Branch is taken
T4 is loaded with new value from memory
T0 increases by 200
What is the total number of instructions that get fully executed?
Multiple choice 4 Question 2
101
12
144
1412
How many cycles it take to execute all instructions in the given code?
Multiple choice 5 Question 2
2136
36
24
576
What is the final value of T0?
Multiple choice 6 Question 2
194
301
201
200

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