Multi$-$Cycle Arch. Given the following code. Assume that $x$ and $y$ are arrays of words and the base address of $x$ is stored in $R1$ and the base address of $y$ is stored in R$2.$ Assume that each add operation takes $3$ cycles to execute, each lw operation $4$ cycles, each store sw takes $3$ cycles, and each branch $($bne$)$ instruction takes $2.$cycles to execute. The $"T"$ represents Temp registers. All numbers are in decimal