Multitasking and Context Switching; Pipelining

Assume a 5-stage pipelined processor using the standard 5-stages (IF, ID, EX, MEM, WB) that uses no forwarding or stalling circuitry. Rather, you will use the compiler to add no-ops to the code to ensure correct execution.

Note: You can assume that if the processor reads and writes to the same register in a given cycle, the value read out will be the new value that is written in that cycle.

Write your own short program that re-writes the code below including the no-ops that are needed to protect against hazard conditions.

add $3, $2, $3 lw $4, 100($3) sub $7, $6, $2 xor $6, $4, $3