need 2.1
2.2.1
2.2.2
2.2.3
2. 50 points Attached is a paper by Namratha et al. The professor who seems to be involved is: Swarnalatha Radhakrishna B.Tech Electronic Engineering IT-BHU), PhD (UNSW). MIEEE (USA), MIEEE-CS (USA) Swamalatha Radhakrishnan received Ph.D. (2007) in Computer Science and Engi neering from the University of New South Wales, Australia and B.Tech (1995) in Electronics and Communication from University of Banaras, India. She was appointed a Senior lecturer at University of Peradeniya in the area of Computer Engineering in December 2007. She is a Member of IEEE Contact Eswarnatice.pdn.ac.k T: +9181233-3913 Research Interests System Level Synthesis of Application Specife Processos Performance, Area and Power Trade-offs of Embedded Process Design Multi-Pipeline Process Design and Synthesis Heterogeneous Pipelines in Embedded Processos URL: http www.cepacks I have presented the above information to demonstrate the qualifications of the person irrespective of the location You are not to contact any of the authors concerning this paper or for help with this examination. A Senior Lecturer in Sri Lanka is roughly the equivalent of a mured Associate Professor in the USA. See URL: https://en.wikipedia.org/wiki/List_of_academic_ranks 2.1. In this course, the concert O am ASIC has been introduced. In addition to an LUR , there is the concept of an ASIP. Define ASTV provide an example of one (typically, an embedded intelligent conta c t o find real world use O web-based resource Article List which references not courtestbook, that you for 2.2. The article is based upon an ARM Thumb instruction set that the authors state is simple and small 2.2.1. List the instructions in the ARM Thumb instruction set, including operand(s) length options 2.2.2. How does the simple and small Thumb ISA compare with that of the current "latest version" full ARM ISA? 2.2.3. Looking at the technical references in the literature, what is the typical phy ical chip size (dimensions and sumber of or connections to the chip) and power consumption of a Thumb s " ARMI? 2.3. The authors make use of two pipelines in their design 2.3.1. What are the two pipelines! 2.3.2. How do the pipelines differ? 2.3.3. What if any hazards would two sach pipelines theoretically present? 2.4. The actual design was implemented using ASIPMeister, one of a number of tools (design applications) used in this research area. Provide a brief overview of ASIP Meister 2.5. Explain what is shown in Figure OL Design Flow of Phase II 2.6. Compare the two tables of measured experimental) results: Table 1: Perfor mance Analysis in Dual-Pipeline and able 2 Performance Analysis in Three Pipeline. In particular, given the implementation presented in the paper, is there a justification for the additional complexity of a three-pipeline versus dual-pipeline
