need # 2.3

2.4.

2.5

2.6

2. [50] pointsAttached is a paper by Navarathna et al. The professor who seems to be involved is: Swarnalatha Radhakrishna B.Tech Electronic Engineering (IT-BHU), PhD (UNSW), MIEEE (USA), MIEEE-CS (USA) Swarnalatha Radhakrishnan received Ph.D. (2007) in Computer Science and Engi- neering from the University of New South Wales, Australia and B. Tech. (1998) in Electronics and Communication from University of Banaras, India. She was appointed a Senior lecturer at University of Peradeniya in the area of Computer Engineering in December 2007. She is a Member of IEEE Contact E: swarna@ce.pdn.ac.lk T: +94.81.239-3913 Research Interests System Level Synthesis of Application Specific Processors: Performance, Area and Power Trade-offs of Embedded Processor Design; Multi- Pipeline Processor Design and Synthesis; Heterogeneous Pipelines in Embedded Processors URL: http://www.ce.pdn.ac.lk/swarna.html I have presented the above information to demonstrate the qualifications of the person irrespective of the location. You are not to contact any of the authors concerning this paper or for help with this examination. A "Senior Lecturer in Sri Lanka is roughly the equivalent of a tenured Associate Professor in the USA. See URL: https://en.wikipedia.org/wiki/List_of_academic_ranks 2.1. In this course, the concept of an ASIC has been introduced. In addition to an ASIC and a general purpose processor of any type of the Flynn Taxonomy, there is the concept of an ASIP. Define ASIP and provide an example of one (typically, an embedded "intelligent" controller). For the example, you will need to find a real world use, typically from a web-based resource article. List which references, not including the course textbook, that you found. 2.2. The article is based upon an ARM Thumb instruction set that the authors state is "simple and small 2.2.1. List the instructions in the ARM Thumb instruction set, including operand(s) length options. 2.2.2. How does the simple and small Thumb ISA compare with that of the current "latest version full ARM ISA? 2.2.3. Looking at the technical references in the literature, what is the typical phys- ical chip size (dimensions and number of pins or connections to the chip) and power consumption of a Thumb versus full ARM? 2.3. The authors make use of two pipelines in their design. 2.3.1. What are the two pipelines? 2.3.2. How do the pipelines differ? 2.3.3. What if any hazards would two such pipelines theoretically present? 2.4. The actual design was implemented using ASIPMeister, one of a number of tools (design applications) used in this research area. Provide a brief overview of ASIP- Meister. 2.5. Explain what is shown in Figure 04: Design Flow of Phase II. 2.6. Compare the two tables of measured (experimental) results: Table 1: Perfor- mance Analysis in Dual-Pipeline and able 2: Performance Analysis in Three- Pipeline. In particular, given the implementation presented in the paper, is there a justification for the additional complexity of a three-pipeline versus dual-pipeline design? 2. [50] pointsAttached is a paper by Navarathna et al. The professor who seems to be involved is: Swarnalatha Radhakrishna B.Tech Electronic Engineering (IT-BHU), PhD (UNSW), MIEEE (USA), MIEEE-CS (USA) Swarnalatha Radhakrishnan received Ph.D. (2007) in Computer Science and Engi- neering from the University of New South Wales, Australia and B. Tech. (1998) in Electronics and Communication from University of Banaras, India. She was appointed a Senior lecturer at University of Peradeniya in the area of Computer Engineering in December 2007. She is a Member of IEEE Contact E: swarna@ce.pdn.ac.lk T: +94.81.239-3913 Research Interests System Level Synthesis of Application Specific Processors: Performance, Area and Power Trade-offs of Embedded Processor Design; Multi- Pipeline Processor Design and Synthesis; Heterogeneous Pipelines in Embedded Processors URL: http://www.ce.pdn.ac.lk/swarna.html I have presented the above information to demonstrate the qualifications of the person irrespective of the location. You are not to contact any of the authors concerning this paper or for help with this examination. A "Senior Lecturer in Sri Lanka is roughly the equivalent of a tenured Associate Professor in the USA. See URL: https://en.wikipedia.org/wiki/List_of_academic_ranks 2.1. In this course, the concept of an ASIC has been introduced. In addition to an ASIC and a general purpose processor of any type of the Flynn Taxonomy, there is the concept of an ASIP. Define ASIP and provide an example of one (typically, an embedded "intelligent" controller). For the example, you will need to find a real world use, typically from a web-based resource article. List which references, not including the course textbook, that you found. 2.2. The article is based upon an ARM Thumb instruction set that the authors state is "simple and small 2.2.1. List the instructions in the ARM Thumb instruction set, including operand(s) length options. 2.2.2. How does the simple and small Thumb ISA compare with that of the current "latest version full ARM ISA? 2.2.3. Looking at the technical references in the literature, what is the typical phys- ical chip size (dimensions and number of pins or connections to the chip) and power consumption of a Thumb versus full ARM? 2.3. The authors make use of two pipelines in their design. 2.3.1. What are the two pipelines? 2.3.2. How do the pipelines differ? 2.3.3. What if any hazards would two such pipelines theoretically present? 2.4. The actual design was implemented using ASIPMeister, one of a number of tools (design applications) used in this research area. Provide a brief overview of ASIP- Meister. 2.5. Explain what is shown in Figure 04: Design Flow of Phase II. 2.6. Compare the two tables of measured (experimental) results: Table 1: Perfor- mance Analysis in Dual-Pipeline and able 2: Performance Analysis in Three- Pipeline. In particular, given the implementation presented in the paper, is there a justification for the additional complexity of a three-pipeline versus dual-pipeline design