Need an explanation of how this verilog code behaves. Commenting what the lines do would be helpful thanks.

Demo.v & demo_tb.v

`timescale 1 ns / 100 ps module demo (count, count_tri, clk, rst_l, load_l, enable_l, cnt_in, oe_l); output [3:0] count; output [3:0] count_tri; input clk; input rst_l; input load_l; input enable_l; input [3:0] cnt_in; input oe_l; reg [3:0] count; // tri-state buffers assign count_tri = (!oe_l) ? count : 4'bZZZZ; // synchronous 4 bit counter always @ (posedge clk or negedge rst_l) begin if (!rst_l) begin count <= #1 4'b0000; end else if (!load_l) begin count <= #1 cnt_in; end else if (!enable_l) begin count <= #1 count + 1; end end endmodule `timescale 1 ns / 100 ps module demo_tb; reg clk_50; reg rst_l, load_l, enable_l; reg [3:0] count_in; reg oe_l; wire [3:0] cnt_out; wire [3:0] count_tri; demo U1 ( .count(cnt_out), .count_tri(count_tri), .clk(clk_50), .rst_l(rst_l), .load_l(load_l), .cnt_in(count_in), .enable_l(enable_l), .oe_l(oe_l) ); // create a 50Mhz clock always #10 clk_50 = ~clk_50; // every ten nanoseconds invert initial begin $display($time, " << Starting the Simulation >>"); clk_50 = 1'b0; rst_l = 0; enable_l = 1'b1; load_l = 1'b1; count_in = 4'h0; oe_l = 4'b0; #20 rst_l = 1'b1; $display($time, " << Coming out of reset >>"); @(negedge clk_50); // wait till the negedge of load_count(4'hA); @(negedge clk_50); $display($time, " << Turning ON the count enable >>"); enable_l = 1'b0; wait (cnt_out == 4'b0001); $display($time, " << count = %d - Turning OFF the count enable >>", cnt_out); enable_l = 1'b1; #40; // let the simulation run for 40ns // the counter should not count $display($time, " << Turning OFF the OE >>"); oe_l = 1'b1; // disable OE, the outputs of count_tri should go high Z. #20; $display($time, " << Simulation Complete >>"); $stop; end initial begin // $monitor will print whenever a signal changes in the design $monitor($time, " clk_50=%b, rst_l=%b, enable_l=%b, load_l=%b, count_in=%h, cnt_out=%h, oe_l=%b, count_tri=%h", clk_50, rst_l,enable_l, load_l, count_in, cnt_out, oe_l, count_tri); end // The load_count task loads the counter with the value passed task load_count; input [3:0] load_value; begin @(negedge clk_50); $display($time, " << Loading the counter with %h >>", load_value); load_l = 1'b0; count_in = load_value; @(negedge clk_50); load_l = 1'b1; end endtask endmodule