Question
Need help with Computer Architecture homework, we're using this book Computer Organization and Design, ARM Edition ISBN 978-0-12-801733-3. Assume we have a 512 byte cache
Need help with Computer Architecture homework, we're using this book Computer Organization and Design, ARM Edition ISBN 978-0-12-801733-3.
Assume we have a 512 byte cache with 64 byte blocks. We also assume that the main memory is 2KB large. We can regard the memory as an array of 64-byte memory blocks M0, M1, M2, M31. The table below displays the memory blocks that can reside in different cache blocks if the cache was fully associative.
Cache Block | Set | Memory blocks that can reside in cache blocks |
0 | 0 | M0, M1, M2, . M31 |
1 | 0 | M0, M1, M2, . M31 |
2 | 0 | M0, M1, M2, . M31 |
3 | 0 | M0, M1, M2, . M31 |
4 | 0 | M0, M1, M2, . M31 |
5 | 0 | M0, M1, M2, . M31 |
6 | 0 | M0, M1, M2, . M31 |
7 | 0 | M0, M1, M2, . M31 |
Show the elements of the table if cache is organized as a direct mapped cache.
Show the elements of the table if cache is organized as a two-way set associative cache.
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