Need help with computer architecure problem.

A. Can Blocks 0, 2 and 4 be in the cache at the SAME time?

YES or NO

B. Can Blocks 0, 1 and 4 be in the cache at the SAME time?

YES or NO

C. Can Blocks 1, 3 and 7 be in the cache at time?

YES or NO

D. Can Blocks 2 and 6 be in the cache at the SAME time?

YES or NO

E. If cache becomes direct mapped, can Blocks 2 and 4 be in the cache at the SAME time?

YES or NO

F. If cache becomes direct mapped, can Blocks 2 and 6 be in the cache at the SAME time?

YES or NO

G. Can Page 0, 1, 2, 6 and 7 be in the Main Memory at the SAME time?

YES or NO

H. Can Page 0, 1, 3, 5 and 7 be in the Main Memory at the SAME time?

YES or NO

I. (15 Pts) Show the address format for virtual address 1816 (specify field name and size) that would be used by the system to translate to a physical address and then translate this virtual

address into the corresponding physical address. (Hint: convert 18₁₆ to its binary equivalent

and divide it into the appropriate fields.) Explain how these fields are used to translate to

the corresponding physical address.

J. Given virtual address 4516.

What frame does the page containing virtual address 4516 maps to?

What physical address does the virtual address 4516 maps to?

Is this a TLB hit?

Is the physical address above in the Cache? If so, what is the set and tag?

K. Given virtual address 2516

What page is the address in?

What is the byte offset?

Is the page in physical memory?

I.You have a byte-addressable virtual memory system with a two-ent ry TLB, a 2-way set associative cache and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 by each block is represented by a letter. Two blocks equals one frame. tes. In the system below, main memory is divided up into blocks, where Block Page Frame TAG DATA TAG DATA A 0 Set 0 00 Set 00 C 2 D 3 E 4 Cache G 6 Frame Valid Block 4 6.M12 G 4 0 15 Virtual Memory For Process P Page Table Main Memory