Need help with part D

Suppose we have a system with the following properties: - The memory is byte addressable - Memory accesses are to 1-byte words (not 4-byte words) - Addresses are 13-bits wide - The cache is 4-way set associative. (E=4), with a 4-byte block size (B=4) and eight sets (S=8) Consider the following cache state. All addresses, tags, and values are given in hexadecimal format. The index column contains the set index for each set of four lines. The Tag column contains the tag value for each line. The V column contains the valid bit for each line. The Bytes 03 columns contain the data for each line, numbered left to right starting with byte 0 on the left. A. What is the size C of this cache in bytes? B. The 13 bits in an address are labeled 0 to 12 with 0 being the low order bit and 12 being the high order bit. Indicate which bits form the following parameters B1. CO the cache block offset B2. Cl the cache set index B3. CT the cache tag C. Suppose that a program using the cache described above references the 1-byte word at address 0x071A. Indicate the cache entry accessed and the cache byte value returned in hex. Indicate whether a cache miss occurs. If there is a cache miss, enter --- for "Cache byte returned." Pay attention to the valid bits