Q3 Suppose we have a system with the following properties . The memory is byte addressable . Memory accesses are to 1-byte words (not to 4-byte words) . Addresses are 12 bits wide . The cache is two-way set associative (E2), with a 4-byte block size (B4 and four sets (S -4) The contents of the cache are as follows, with all addresses, tags, and values given in hexadecimal notation: Set index Tag Valid Byte 0 Byte1 Byte 2 Byte3 40 FE 42 CC 43 DO 831 97 45 46 47 830 48 49 4A 4B 40 0 FF1 9A CO 03 (a) {2 marks) The following diagram shows the format of an address (one bit per box). Indicate (by labelling the diagram) the fields that would be used to determine the following The cache block offset The cache set index . The cache tag (b) 14 marks) For each of the following memory accesses indicate if it will be a cache hit or miss when carried out in sequence as listed. Also give the value of a read if it can be inferred from the information in the cache Operation Address Hit? Read value (or unknown) Read Write Read 0x834 0x836 0xFFD