Need help with this Verilog code. Please include updated code and screenshots. I started it but its not working .

The intent of this project is to produce a design for a traffic light controller using Verilog hardware description language (HDL). This traffic controller will be modeled as a state machine and will control the traffic lights at the four-way intersection. When the light is green on A Street and a car is waiting on B Street, give A Street a yellow light for one clock cycle and then give A Street a red light and B Street a green light for at least two cycles. When the light is green on A Street and there is no car on B Street, leave the light green on A Street. When the is green on B Street (and weve finished the two cycles from step 1) and a car is waiting on A Street, give B Street a yellow light for one clock cycle and then give B Street a red light and A Street a green light for at least two cycles. When the light is green on B Street and there is no car on A Street, leave the light green on B Street. When you press the reset switch, after no more than six cycles, the light should be initially green on A Street and red on B Street and the controller should be ready for operation.

Heres what I have so far but its not working-

module TrafficLight (R, C, clk, T, rstT, S, HW, FR); input wire R, C, clk; input reg T; output wire rstT; output reg [2:0] S, HW, FR; initial begin S = 0; rstT = 1; end always @ (S,R) if (R == 0) S = 0; always @ (posedge clk) endmodule

module Clock (clk); output reg clk; parameter FREQ = 100000; // in kHz parameter DUTY = 50; // in % integer clk_pd = 1/(FREQ * 1e3)*1e9; // convert to ns integer clk_on = DUTY/100 * clk_pd; integer clk_off = (100 - DUTY)/100 * clk_pd; initial clk <= 1;

always begin #(clk_on) clk <= 0; #(clk_off) clk <= 1; end endmodule

module Counter (clk, rst, count); input wire clk, rst; output reg [3:0] count; initial count = 0; always @ (posedge clk, rst) begin if (rst) count <= 0; else count <= count + 1; end endmodule