Need VHDL code for this question on Vivado 2021.1

Rotating and shifting Machine Introduction The aim of this task is to design a digital circuit which rotates a 4-bit input vector by a varying amount. Your design must adapt to the entity declared below. library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity seven_seg_driver is port ( Rotateleft : in std_logic; en : in std_logic; N : in std_logic_vector(1 downto 0 ); Din : in std_logic_vector(3 downto 0); ) ; end seven_seg_driver; The input is applied on the port Din. The number of bits to rotate by is programmed on port N. if RotateLeft is ' 1 ', the Dout should be rotated left, otherwise right. If Enable is ' 0 ', the output on Dout should be the same as the input. Please follow the table below for further information. You are required to simulate your design using testbench. The test bench has OK signal, which should remain true. Synthesize your design to make sure the circuit does not produce any latches. The design must be critically analysed