NO.3 DESIGN AND BEHAVIOURAL SIMULATION OF A STATE MACHINE By modifying the 3-bit binary counter in the pre-lab task, design an FSM-based password unlock unit as shown in Figure 2.1 using Moore state machine. The state in the unit will move from initial state (state 0) to the final state (state 7) when correct password are keyed in correctly for each of the stage. Each state has two directions it can follow and it depends on input from the KEY entered by the user. The KEY is a 3 slide switches (represents 3-bit binary). The unit can be unlocked if correct password i.e. (7654321) are keyed in accordingly. Incorrect password shall not unlock the unit and the state remains in its current state until correct number entered by the user. Assume that the unit is positive edge CLK triggered with synchronous RESET. The unit IDLE state is state 0 and FINISH at state 7. Whenever the RESET is triggered to LOW, the state backs to IDLE state and state 7 (FINISH) is achieved when correct numbers are keyed in. The STATE_OUT bus displays the current state. Based on the specifications given, design the Verilog HDL code, simulate the design and verify its behavioral functionality