Objective: The primary objective of this project to write behavioral model of a bare minimum computer system DaVinci v$1\mathrm{.}0$ supporting instruction set cs$147$DV$.$

To implement a behavioral model of a computer system with a $32-$bit processor and $256$MB memory $($Double word $(32-$bit$)$ addressable $64$M address$).$ The processor supports the instruction set cs$147$DV as described in lecture $01.$

To implement test for the implemented system DaVinci v$1\mathrm{.}0.$

Outcome: Fully functional processor supporting instruction set of $\text{'}$CS$147$DV$\text{'}$ instruction set.

Fully functional $64$MB memory model with data pre$-$loading capability.

Fully functional system integrating memory and the processor. We call this bare minimum computer system as DaVinci v$1\mathrm{.}0.$

Full testing of DaVinci v$1\mathrm{.}0$ with small program using cs$147$DV instruction set.

Complete behavioral model of REGISTER$\_$FILE$\_32$x$32$ in register$\_$file.v

Review MEMORY$\_64$MB in memory.v to understand how to describe register file.Only a few behavior change from memory.$$Test your implementation by simulating RF$\_$TB block.

Complete behavioral model of CONTROL$\_$UNIT in control$\_$unit.v

Test your implementation by simulating DA$\_$VINCI$\_$TB$.$This simulation will create following files in OUTPUT directory.

fibonacci$\_$mem$\_$dump..datRevFib$\_$mem$\_$dump.dat

$//$ Name: register$\_$file.v

$//$ Module: REGISTER$\_$FILE$\_32$x$32$

$//$ Input: DATA$\_$W : Data to be written at address ADDR$\_$W

$//$ ADDR$\_$W : Address of the memory location to be written

$//$ ADDR$\_$R$1$ : Address of the memory location to be read for DATA$\_$R$1$

$//$ ADDR$\_$R$2$ : Address of the memory location to be read for DATA$\_$R$2$

$//$ READ : Read signal

$//$ WRITE : Write signal

$//$ CLK : Clock signal

$//$ RST : Reset signal

$//$ Output: DATA$\_$R$1$ : Data at ADDR$\_$R$1$ address

$//$ DATA$\_$R$2$ : Data at ADDR$\_$R$1$ address

$//$

$//$ Notes: $-32$ bit word accessible dual read register file having $32$ regsisters.

$//-$ Reset is done at $-$ve edge of the RST signal

$//-$ Rest of the operation is done at the $+$ve edge of the CLK signal

$//-$ Read operation is done if READ$=1$ and WRITE$=0$

$//-$ Write operation is done if WRITE$=1$ and READ$=0$

$//-$ X is the value at DATA$\_$R$*$ if both READ and WRITE are $0$ or $1$

$//$

$//$ Revision History:

$//$

$//$ Version Date Who email note

$//------------------------------------------------------------------------------------------$

$//1\mathrm{.}0$ Sep $10,2014$ Kaushik Patra kpatra@sjsu.edu Initial creation

$//------------------------------------------------------------------------------------------$

$//$

$`$include $"$prj$\_$definition.v$"$

module REGISTER$\_$FILE$\_32$x$32($DATA$\_$R$1,$ DATA$\_$R$2,$ ADDR$\_$R$1,$ ADDR$\_$R$2,$

DATA$\_$W$,$ ADDR$\_$W$,$ READ, WRITE, CLK$,$ RST$)$;

$//$ input list

input READ, WRITE, CLK$,$ RST;

input $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ DATA$\_$W;

input $[`$REG$\_$ADDR$\_$INDEX$\_$LIMIT:$0]$ ADDR$\_$R$1,$ ADDR$\_$R$2,$ ADDR$\_$W;

$//$ output list

output $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ DATA$\_$R$1$;

output $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ DATA$\_$R$2$;

always @ $($negedge RST or posedge CLK$)$

begin

$//$ TBD: Code for the register file model

end

endmodule