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Ok so i have VHDL code written for an arithmentic logic shift unit; i have created it into a symbol file in quartus 2. I

Ok so i have VHDL code written for an arithmentic logic shift unit; i have created it into a symbol file in quartus 2. I also have a hex display bsf from previous lab. Since it is so confusing to me on trying to use LEDS for thes outputs and the 2 6 bit inputs A and B with a carry in (which i dont think is needed), any help on connecting these two together would be much appricieated.!!!!!! this is on a cyclone DE2-115 board if it helps. right now i have my 6bit A and B take switches up 0-11 sw12 is my Cin and outputs are the 0-5 green leds, well and i guess you can tell bt code a little but the S i used sw14-17 and My'carryflag" is grennled8......

the vhdl code is for the arithmetic logic unit, some of the pic overlapped, just wanted to show how i ended the process.......IF i should stick with leds and maybe just changethem around to make the answers better to understand then by all means suggest that. THANK YOU

and the hex i made using a bunch of logic gates but does 0-9 and A through Fimage text in transcribed.image text in transcribedimage text in transcribedimage text in transcribed

LIBRARY ieee USE ieee. std-logic-1164. a11; USE ieee.std_logic_unsigned.all use ieee.Numeric std.all; ENTITY lab7 IS generic (constant N: natural := 1); PORT CCin : in std_logic; S : IN STD_LOGIC_VECTOR (3 DOWNTO 0); A,B : IN STD_LOGIC_VECTOR (5 DOWNTO 0); Cout out std_logic; F Out: OUT STD_ LOGIC VECTOR (5 DOWNTO 0)); END 1ab7; ARCHITECTURE Behavior OF 1ab7 IS signal F: STD_1ogic vector(5 downto 0); signal tmp std_logic vector (6 downto 0); Begin rocess (A,B,S,Cin) BEGIN CASE (S) IS WHEN "0000" -> F F F F F F F F F F F F F F F F F F F F F F F F F F F F

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