On an ARMv7-M processor, assuming that [R1] = 0x010E0C2D, [R2] = 0x941BC081, [N-bit] = 1, [Z-bit] = 1, [C-bit] = 0, [V-bit] = 1, predict the 32-bit [R1] and all four condition flags in CPSR after an ARM comparison instruction is executed in EACH case. (These instructions are NOT executed one after the other one; instead, each instruction starts with the initial conditions given in the statement.)

(a) CMP R1, #0xE9

(b) TEQ R1, R2

(c) CMN R1, R2, RRX

(d) TST R1, R2, LSL #0x10