One common programming test is fizzbuzz. The fizzbuzz program should output the first 100 integers, any integer which is a multiple of 3 should print fizz, any integer which is a multiple of 5 should print buzz, any integer a multiple of 3 and 5 should print fizzbuzz, the remaining integers should print their value. The verilog module fizzbuzz.v contains fizzbuzz4( fizz, buzz, fizzbuzz, num ) and fizzbuzz5( fizz, buzz, fizzbuzz, num ). fizzbuzz4 provides a 4-bit number input, num and three outputs. fizz is true if num is a multiple of 3, buzz is true if num is a multiple of 5, and fizzbuzz is true if num is a multple of 3 and 5. fizzbuzz5 accepts 5 bit numbers. The module, tb_fizzbuzz.v provides a test bench for fizzbuzz4 and fizzbuzz5. Once downloaded the modules are tested with: iverilog tb_fizzbuzz.v fizzbuzz.v && vvp a.out Replace the behavioural coding in fizzbuzz4 with Boolean Expressions. The fizzbuzz5 behavioural must also be replaced. It can be implement with two four variable modules. One module handles the numbers from 0 to 15, and the other module handles 16 to 31. Since fizzbuzz4 already handles 0 to 15 it can be used in fizzbuzz5.

fizzbuzz.v:

`timescale 1ns / 1ns module fizzbuzz4( fizz, buzz, fizzbuzz, num ); output fizz, buzz, fizzbuzz; input [3:0] num; // replace the behvaioural description with // gates or boolean expressions, // a 4 variable truth table and K-map can be used to design // each of fizz and buzz. assign fizz = (num%3) == 0; assign buzz = (num%5) == 0; assign fizzbuzz = fizz & buzz; endmodule module fizzbuzz5( fizz, buzz, fizzbuzz, num ); output fizz, buzz, fizzbuzz; input [4:0] num; // replace the behvaioural description with // gates or boolean expressions, // fizzbuzz4 handles 0 to 15, a second four variable // truth table can be constructed for num from 16 to 31 // these two modules (0 to 15) and (16 to 15) can be combined // with a MUX assign fizz = (num%3) == 0; assign buzz = (num%5) == 0; assign fizzbuzz = fizz & buzz; endmodule 

tb_fizzbuzz.v:

`timescale 1ns / 1ns module fizzbuzz_behave( fizz, buzz, fizzbuzz, num ); parameter N = 4; output fizz, buzz, fizzbuzz; input [N-1:0] num; assign fizz = (num%3) == 0; assign buzz = (num%5) == 0; assign fizzbuzz = fizz & buzz; endmodule module main; integer all_bits; integer pass; wire f4_test, b4_test, fb4_test; wire f5_test, b5_test, fb5_test; wire f_behave, b_behave, fb_behave; fizzbuzz5 test5( f5_test, b5_test, fb5_test, all_bits[4:0] ); fizzbuzz4 test4( f4_test, b4_test, fb4_test, all_bits[3:0] ); fizzbuzz_behave #(5) fb_behave_test( f_behave, b_behave, fb_behave, all_bits[4:0] ); initial begin all_bits = 0; pass = 1; repeat ( 16 ) begin #10; if ( f4_test != f_behave || b4_test != b_behave || fb_behave != fb4_test ) begin $display("fizzbuzz4 test failed at %2d", all_bits); pass = 0; end all_bits = all_bits + 1; end if ( pass == 1 ) $display( "fizzbuzz4 passed"); all_bits = 0; pass = 1; repeat ( 32 ) begin #10; if ( f5_test != f_behave || b5_test != b_behave || fb_behave != fb5_test ) begin $display("fizzbuzz5 test failed at %2d", all_bits); pass = 0; end all_bits = all_bits + 1; end if ( pass == 1 ) $display( "fizzbuzz5 passed"); end endmodule