One CPU manufacturer proposed the 10-stage pipeline below for a 500MHz (2ns clock cycle) machine Here are the correspondences between this and the MIPS pipeline: Instructions are fetched in the FET stage Register reading is performed in the REG stage. ALU operations and memory access are both done in the EXE stage. Branches are resolved in the DET stage. WRB is the write back stage. How much time is required to execute one million instructions on this processor, assuming there are no dependencies or branches in the code? (3%) Without forwarding, how many Assume that the register file could be written and read in the same clock cycle. What is this hazard called? (3%) If a branch is mispredicted, how many instructions would have to be flushed from the (3%) pipeline? Assume that a program executes one million instructions. Of these, 15% are load instructions which stall, and 10% of the instructions are branches. The CPU predicts branches correctly 75% of the time, How much time will it take to execute this program