One of the functions an ALU in a CISC processor supports is high speed addition. You are given only

two types of building blocks. $(1)$ Full adder: delay $0\mathrm{.}8$ ns $(2)$ D Flip$-$Flop: Set up time: $0\mathrm{.}1$ ns; hold time: $0$

ns; clock$-$to$-$output delay: $0\mathrm{.}1$ ns$.$

Using these building blocks, design optimal hardware architecture, to perform addition operation on two

unsigned sixteen$-$bit binary numbers, with a sustained throughput of one sixteen$-$bit addition per clock

cycle, at the clock rate of $500$ MHz$.$