Only b

(20 pts.) Design a state diagram to perform the following function. There are two data inputs A and B, a check input C, and an output D. The FSM takes as input two continuous synchronous streams of 4-bit two's complement numbers in a bit-serial form with the most significant (sign) bit first. The least significant bit is marked by a 1 on the check line (C). During the time slot in which C is asserted, the output D should go to a 1 if the two's complement number on A is larger than the two's complement number on B. a. b. (16 pts.) Complete the below simulation waveforms 0 D o