Our goal is to design a traffic-light controller with the following properties; it lights up the green light (output G) for 24 seconds, followed by the yellow light (output Y) for 4 seconds, then the red light (output R) for 32 seconds. The controller will repeat this pattern forever. Our system will have a clock signal with a period of 4 seconds.

1. How many states, N, are needed in a FSM to implement this controller? In how many of these states will the light be green, yellow, and red, respectively? What is the minimum number of state bits, M, needed to implement this controller?

2. Draw the state diagram for a FSM implementing this controller. Label states in which the light is green as GREEN1, GREEN2, and so on, yellow as YELLOW1, and so on, red as RED1, and so on.

3. You will implement this FSM using a special down-counter that is available to you as a "black-box" circuit element. This M-bit counter (of the same minimum size you determined in Part 1) has the following properties: it normally counts down in binary by 1 each clock cycle; (2) after counting down to 0 (and holding that for the usual 1 clock period) it parallel loads as the next state the bit pattern L[M-1],...,L2,L1,L0, and then continues counting down from there. Otherwise, it ignores the Lx inputs. This device thus has outputs Q[M-1],...,Q2,Q1,Q0, and inputs CLK and L[M-1],...,L2,L1,L0. In your solution, draw it as a rectangular box with CLK (positive-edge-triggered) entering from the top, the Lx inputs entering on the left side, and the Qx outputs on the right side, just like the picture below: Problem2_0.png?version=1&modificationDat Assign the highest-numbered needed binary values (N?1, N?2, ...) to your green-light state(s), the next to your yellow state(s), and the lowest (...,2,1,0) to the red-light states. Based on this assignment, write the Karnaugh-maps for the three outputs G, Y, and R. Rather than filling unneeded state(s) with don't cares, choose a light color that ensures safe traffic control if the counter somehow enters an undefined state, and briefly explain why you chose what you did. Come up with expressions for each output that minimize area (use sum of literals and operators to approximate area). Consider SOP, POS, and using outputs to define other outputs. If you're careful, you can get the design down to four inverters and four larger gates (in addition to the down-counter). Sketch the circuit diagram for your solution, using the special down-counter as a circuit element that is already given to you; draw it as described above. (Points will be deducted for not using or not drawing this element as described!)