Ox1006 Ox1007 Ox00 Ox00 c) What is the maximum performance improvement that can be gained by a CPU with a 3-stage CPU pipeline with single clock cycle instructions (assuming no data and control dependencies) over a CPU with no pipeline assuming that the CPU with no pipeline that requires 3 clock cycles to complete a single instruction? Please show your work. d) Please write an ARM instruction that will update the NZCV bits of CPSR register as 0100: e) If the current program counter value if Ox1400 then the instruction B #20 will update the program counter value to: Page 2 of 5