P5-1: (using Verilog generate statement) Sketch the functional block diagram of the following Verilog design that uses a generate construct. modulo DU (input clk, rst, mi, mo, Input (3:0) id, output [30] Aout ), rog (3:0) oe, R[0:31: wiro (3:0) Abus ; always @ (posedge clk) bogin for (k0; k