Question
Page 3, 4, 5: Instruction Set Analysis and CPU Architecture We need to develop an instruction set, formats, and CPU architecture to support the following
Page 3, 4, 5: Instruction Set Analysis and CPU Architecture
We need to develop an instruction set, formats, and CPU architecture to support the following operations:
R1 R1 OP R2: 32 instructions
R3 R1 OP R2: 32 instructions
MEM R1: 32 instructions
MEM R1 OP R2: 16 instructions
R2 R1 OP MEM: 16 instructions
The machine has 16 general purpose registers, each 16 bits in size. Memory is accessed by a base plus displacement of 12 bits.
Page 3: Analysis. Page 4: Instruction Formats. Page 5 CPU internal design.
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Spatio Temporal Database Management International Workshop Stdbm 99 Edinburgh Scotland September 10 11 1999 Proceedings Lncs 1678
Authors: Michael H. Bohlen ,Christian S. Jensen ,Michel O. Scholl
1999th Edition
3540664017, 978-3540664017
