Part $1$: BasicsPart $1$: Basics

Explore and understand the performance implications of

Explore and understand the performance implications of different cache and memory configurations on x$86$

architectures using GEM$5$ simulation tools. This part involves two main questions, Q$-1$A and Q$-1$B$,$ centered

around a matrix multiplication C program.

$$ Simulation Tool: GEM$5$ Simulator

$$ Programming Language: C and GCC compiler; C$++$ and G$++$ compiler

$1\mathrm{.}1$ Clock Frequency and CPI Analysis

Task: Analyze the Cycles Per Instruction $($CPI$)$ under varying clock frequencies for two different architectural

setups using the Matrix Multiplication $($C$++)$ Implementation provided at the end of the document with the

two default architecture configurations.

$$ Setup $1$: x$86$ architecture without any cache hierarchy.

$$ Setup $2$: x$86$ architecture equipped with L$1$ and L$2$ cache hierarchies.

Procedure:

$1.$ Configure the GEM$5$ simulator to run the matrix multiplication program on both setups.

$2.$ Modify the clock frequencies of the processor in gradual increments $($suggest specific ranges, e$.$g$.,$ from $1$

GHz to $4$ GHz in steps of $0\mathrm{.}5$ GHz$).$

$3.$ Collect and report the CPI for each frequency setting for both setups.

$4.$ Analyze how the presence or absence of cache hierarchies affects the CPI as the clock frequency changes.

What to report:

$$ Document the relationship between clock frequency and CPI for both configurations with a detailed Table

or Figure $($plot$)$

$$ Discuss in details about the impact of cache hierarchies on CPI.

$1\mathrm{.}2$ Memory Controller Modification

Task: Investigate the effects of different memory controllers on system performance by replacing the DDR$3$

memory controller with a DDR$4$ memory controller in the GEM$5$ simulation.

Procedure:

$1.$ Set up the matrix multiplication program to run on an x$86$ architecture with a standard DDR$3$ memory

controller.

$2.$ Replace the DDR$3$ controller with a DDR$4$ controller and re$-$run the simulation $($system$.$mem ctrl$.$dram

$=$ DDR$424008$x$8())$

$3.$ Redo the explorations of $1\mathrm{.}1$ of clock configuration.

$4.$ Compare the performance metrics, focusing on memory access times and overall execution time.

What to report:

$$ Report on any observed differences in performance with the DDR$3$ vs$.$ DDR$4$ memory controllers. Provide

insights into how memory technology impacts computational efficiency and system performance. Explain

your observations from the architecture design and execution point of view why you observe a significant

performance improvements, or explain why there is no significant improvements.

$1$

$2$ Part $2$: Cache Design Space Exploration

Note: In part $2,$ you will fix frequency at $1$ GHz$.$

$2\mathrm{.}1$ Cache Associativity and CPI Performance

Task: Explore the impact of different associativity configurations in L$1$ and L$2$ caches on the CPI performance

for a matrix multiplication program. Cache associativity is a crucial factor in determining the cache hit rate,

which in turn affects the overall performance of the processor. Students will investigate how changes in the

associativity of L$1$ and L$2$ caches influence the execution performance of a given computational task.

Default Configuration $($caches$.$py$)$:

$$ L$1$ Cache Associativity: $2$

$$ L$2$ Cache Associativity: $8$

Procedure:

$1.$ Configure the initial GEM$5$ simulation environment using the default cache settings for the matrix mul$-$

tiplication C program.

$2.$ Systematically vary the associativity of L$1$ and L$2$ caches. For L$1,$ test associativities of $1,2,4,$ and $8.$

For L$2,$ test associativities of $2,4,8,$ and $16.$

$3.$ Run simulations for each configuration and collect data on CPI performance.

$4.$ Use Table or Figure $($Plot$)$ methods to compare the CPI results across different cache associativity settings.

What to report:

$$ Provide a detailed analysis of how L$1$ and L$2$ cache associativities affect the CPI for the matrix multipli$-$

cation program.

$$ Discuss the trade$-$offs involved in increasing or decreasing cache associativity, considering aspects like

cache hit rate, latency, and overall system performance. For the hardware cost estimation $($quantitative

analysis is needed$),$ please refer to lecture$12.$

$$ Conclude with recommendations on optimal cache associativity settings based on the simulation results.

$2\mathrm{.}2$ Cache Associativity and CPI Performance Analysis Across Programs

Task: Investigate how variations in cache associativity affect the CPI performance when running a Fibonacci

sequence computation program. Different programs exhibit varying behaviors and sensitivities to cache design

due to their unique memory access patterns. This part of the project aims to show students how the performance

impact of cache configurations can differ across applications by using a Fibonacci sequence calculation as a new

test case.

Procedure:

$1.$ Configure the GEM$5$ simulator with the default cache settings $($L$1$ associativity of $2,$ L$2$ associativity of

$8)$ to run the provided Fibonacci sequence C program.

$2.$ Modify the cache settings by testing the same associativities as in Q$-2$A $($L$1$ associativities of $1,2,4,8$

and L$2$ associativities of $4,8,1$