Part 1, SR Latch A latch is a device with exactly two stable states: high-output and low-output. A latch has a feedback path, so that information can be retained by the device. Latches are volatile memory devices, storing one bit of data for as long as the device is powered. The name suggests that latches are used to "latch onto" information and store it in place. An SR latch (Set/Reset) is an asynchronous device, working independently of control signals, relying only on the state of the S and R inputs. SET: an input that makes the device store a logic 1; RESET: an input that makes the device store a logic 0. 1 0 1 0 R (reset) S (set) (a) Logic diagram Equation: S=R=0 Q' The behavior of an SR latch: When S is high, a 1 is stored to Q; When R is high, a 0 is stored to Q; When both are low, the previous state is preserved; (Hence, known as a storage or memory element.) When both are high, the output is unstable. DO NOT set both inputs are high! In this case, both Q and Q' are 0. When both R and S are set to 1, we cannot decide the output Q should be 1 or 0 because the delay of these two and-not gates is not defined. S=1 R=0 Set Q=0 Assign R to SW[0] and LEDR[0]; Assign S to SW[1] and LEDR[1]; Assign Q to LEDR[2], Q' to LEDR[3]; SRQQ' 00 01 (after S = 0, R = 1) 1 1 0 0 (forbidden) (b) Function table Q=1 a. Write a Verilog module to implement an SR latch. b. Program it to the Altera board. i. ii. 1 0 10 0 0 1 0 (after S= 1, R = 0) 0101 Reset S=0 R=1 Qn+1 = S+RQ" also S' + R' = 1 (This is the protected condition) c. Take photos for the first four cases in the true table above; d. Name your code as 'sr_latch'. S=R=0