Part 3: Name Performance Evaluation, Pipelining. Cache and Each block contains 8 ward 32 bit address set-associative words, Each word cpace. The LI cache has 25 blocks 2. How many sets will there be in 2. How many bits will there be in the cache? rag? 3. The level 2 cache in the above computer has 1MB How many blocks does the level 2 cache hold? 4. Forwarding the ALU a) structural hazards result to 5. It is possible to eliminate all delays in the execut on of branch hazards pipeline through hardware and software improvemen of statements through the CPI of 1.0 (once the pipeline is loaded). a) True b) False 6. When a new program is executed, what happens to the data in the CAT? a) both valid and dirty bits =0 c) valid bits =0, dirty bits =1 b) valid bits =1, dirty bits =0 d) both valid bits and dirty bits =1 7. Your cache implements the "write-through" protocol. On a "hit" and "STORE", a) the dirty bit is set to 1 b) the dirty bit is set to 1 until the main memory completes writing, then reset to 0 c) write-through does not require the use of a dirty bit 8. To improve the overall number of "hits" in cache performance, the most effective change to the memory design is to increase the word size. a) TRUE b) FALSE 9. Which CAT mapping usually gives the best hit-miss ratio most efficiently? a) direct mapping b) set-associative implementation c) fully associative 10. Which CAT mapping gives the most complete usage of the cache? a) direct mapping b) set-associative implementation c) fully associative 3. 4 ninate 5. 5. 6. 7. 8. 9. 10