Part I Consider the circuit in Figure 1. It is a 4bit synellmnous counter which uses four Ttype ipops. The collnter increments its value can each positive edge of the clock if the Enable signal is asserted. The counter is reset to 0 by setting the Clear signal low. You are to implement a 3bit counter of this type. Clear Figure 1: A 4bit counter. 1. Write a Verilog le that denes a 8bit counter by using the structure depicted in Figure 1. Your code should include a T ipop module that is instantiated 8 times to create the counter. Compile the circuit. How many logic elements (LEs) are used to implement your circuit? What is the maximum equency, Fm\