Part2: Handling Cache Miss

Question 3 (20 pt). You purchased a computer with the following features:

95% of all memory accesses are found in the cache.

Each cache block is two words, and the whole block is read on any miss.

The processor sends references to its cache at the rate of 109 words per second.

25% of those references are writes.

Assume that the memory system can support 109 words per second, reads or writes.

The bus reads or writes a single word at a time (the memory system cannot read or write two words at once).

Assume at any one time, 30% of the blocks in the cache have been modified.

The cache uses write allocate on a write miss.

You are considering adding a peripheral to the system, and you want to know how much of the memory system bandwidth is already used.

Calculate the percentage of memory system bandwidth used on the average in the two cases below. Be sure to state your assumptions.

a. Case 1: The cache is write through.

b. Case 2: The cache is write back.

Question 4 (10 pt). One difference between a write-through cache and a write-back cache can be in the time it takes to write. During the first cycle, we detect whether a hit will occur, and during the second (assuming a hit) we actually write the data. Lets assume that 50% of the blocks are dirty for a write-back cache. For this question, assume that the write buffer for the write through will never stall the CPU (no penalty). Assume a cache read hit takes 1 clock cycle, the cache miss penalty is 50 clock cycles, and a block write from the cache to main memory takes 50 clock cycles. Finally, assume the instruction cache miss rate is 0.5% and the data cache miss rate is 1%.

Assuming that on average 26% and 9% of instructions in the workload are loads and stores, respectively, estimate the performance of a write-through cache with a two-cycle write versus a write-back cache with a two-cycle write.