4. Extend the following table for Modules 2 and 3. Module 0 Module 1 Module 2 Module 3 0 8 16 24 9 17 25 Module Module O Module 1 2 10 18 26 2 bits Offset in Module Decimal Word Address 0 8 16 24 1 11 19 27 17 25 Binary Address 00000 01000 10000 11000 00001 01001 10001 11001 Module 4 -5 bits- 4 12 20 28 Address Split per Given Structure 3 bits Module Number 00 000 01 000 10 000 11 000 00 001 Module 5 01 001 10 001 11 001 5 13 21 29 Offset in Module 0 1 2 3 0 1 2 3 Module 6 6 14 22 30 Module Number 0 0 0 0 1 1 Module 7 7 15 23 31 c) a) Low-Order Memory Interleaving b) Address Structure c) First Two Modules