please answer 1 and 2 they are part of one question

1) Write VHDL descriptions for components that implement the following functions. Note that each component will have in inputs A, B, C, and D, and a single output, F1 (or F2, F3, F4). F1(A,B,C,D)= '1'if and only if at least one input = '1' and at least another input = '0'. F2(A,B,C,D) = 'l' if and only if three of the inputs = '1'. F3(A,B,C,D) = '1' if and only if the number of inputs that = '1' is even. F4(A,B,C,D) = {m(0.1.2.4,5,6,8,9,11,12,14) F1 F2 AB CD 00 00 01 11 10 AB CD 00 00 01 11 10 01 01 11 11 10 10 F4 F3 AB 0001 00 11 10 AB CD 00 01 11 10 00 01 01 11 11 10 10 2) Write a VHDL test bench (or multiple test benches) to test the VHDL descriptions you developed for 1). Simulate each model and its test bench to demonstrate correct operation. 1) Write VHDL descriptions for components that implement the following functions. Note that each component will have in inputs A, B, C, and D, and a single output, F1 (or F2, F3, F4). F1(A,B,C,D)= '1'if and only if at least one input = '1' and at least another input = '0'. F2(A,B,C,D) = 'l' if and only if three of the inputs = '1'. F3(A,B,C,D) = '1' if and only if the number of inputs that = '1' is even. F4(A,B,C,D) = {m(0.1.2.4,5,6,8,9,11,12,14) F1 F2 AB CD 00 00 01 11 10 AB CD 00 00 01 11 10 01 01 11 11 10 10 F4 F3 AB 0001 00 11 10 AB CD 00 01 11 10 00 01 01 11 11 10 10 2) Write a VHDL test bench (or multiple test benches) to test the VHDL descriptions you developed for 1). Simulate each model and its test bench to demonstrate correct operation