please answer all 3 of these questions with explanation. Thanks!

Section 5.5: Modeling Concurrent Func- tionality in VHDL 5.5.1 Design a VHDL model to implement the behav- ior described by the 3-input minterm list shown in Fiq. 5.11 Use concurrent sianal assignments and logical operators. Declare your entity to match the block diagram provided. Use the type bit for your ports. SystemE.vhd FZAB.c(1,3,4,6) B Fig. 5.11 System E Functionality 5.5.8 5.5.2 Design a VHDL model to implement the behav- ior described by the 3-input minterm list shown in Fig. 5.11. Use conditional signal assignments. Declare your entity to match the 5:5.9 block diagram provided. Use the type bit for your ports Design a VHDL model to implement the behav- ior described by the 3-input minterm list shown in Fig. 5.11. Use selected signal assignments. Declare your entity to match the block diagranm provided. Use the type bit for your ports. 5.5.3 5.5.10