Please answer ALL PARTS:

1. (2 pts) For a 4KiB page, and a 32 bit address space, calculate the amount of memory needed to store a process's page tables. Assume each entry in the page table requires 12 bytes. Show all calculations.

2. (2 pts) For a 4KiB page, and a 64 bit address space, calculate the amount of memory needed to store a process's page tables. Assume each entry in the page table requires 12 bytes. Show all calculations.

3. (2 pts) For a 16KiB page, and a 32 bit address space, calculate the amount of memory needed to store a process's page tables. Assume each entry in the page table requires 12 bytes. Show all calculations.

4. (2 pts) For a 16KiB page, and a 64 bit address space, calculate the amount of memory needed to store a process's page tables. Assume each entry in the page table requires 12 bytes. Show all calculations.

5. (6 pts) Suppose the existence of an associative cache design with N 2. Assume that the main memory uses a 32-bit address (and that each address maps to a single byte). If the cache scheme uses the following breakdown of the address bits: Index 5-3 Tag Offset 31-6 a. What is the cache block size (in words)? b. How many block indices does the cache have? c. Including space for the valid bits, tags, and actual block data, how many bits would be required to actually implement this hypothetical cache? 6. (10 pts) Using the cache design from the previous problem, assume the following byte-addressed cache references are recorded. Assume that the cache is initially empty. Also assume that accesses occurred from left to right (e.g. address 0 was requested, then address 4, followed by address 16, etc) Byte Address 4 1 6 132 232 T 160 1024|30 | 140 3 100 180 2180 What was the number of cache hits? Create a table to show the final state of the cache including the value of each index, the valid bits, and the tags. a. b