Question
Please check my work to this question and point out errors I have made. Thank you! : Consider a 3-processor multiprocessor connected with a shared
Please check my work to this question and point out errors I have made. Thank you! :
Consider a 3-processor multiprocessor connected with a shared bus that has the following properties: (i) centralized shared memory accessible with the bus, (ii) snooping-based MSI cache coherence protocol, (iii) write-invalidate policy. Also assume that the caches have a writeback policy. Initially, the caches all have invalid data. The processors issue the following five requests, one after the other.
My Answer so far:
Request | Cache Hit/miss | Request on the bus | Who Responds | State in Cache 1 | State in Cache 2 | State in Cache 3 |
Invalid | Invalid | Invalid | ||||
P1: Read X | Miss | Read X | Memory | Shared X | Invalid | Invalid |
P1: Write X | Permission Miss | Upgrade X | No response | Modified X | Invalid | Invalid |
P3: Read X | Miss | Read X | P1 responds + Memory Writeback | Shared X | Invalid | Shared X |
P2: Read X | Miss | Read X | Memory | Shared X | Shared X | Shared X |
P3: Write X | Permission Miss | Upgrade X | No response + other caches invalidate | Invalid | Invalid | Modify X |
Step by Step Solution
There are 3 Steps involved in it
Step: 1
Get Instant Access to Expert-Tailored Solutions
See step-by-step solutions with expert insights and AI powered tools for academic success
Step: 2
Step: 3
Ace Your Homework with AI
Get the answers you need in no time with our AI-driven, step-by-step assistance
Get Started