Please correct my following computer architecture question regarding pipelines and registers

Consider the following sequence of instructions executed on the pipelined datapath below. Assume that the IF stage of the first instruction is executed during cycle 1. Indicate the width and contents of the fD/EX pipeline register as it should be at the end of cycle 4. If the value cannot be determined, place a *?* in the entry. If the value is inconsequential, place an "X" in the entry. Since the multiplexors are not mapped to input selector values, assume that the topmost input is selected with value 0, the input below that is selected with value 1, etc. Consider the following sequence of instructions executed on the pipelined datapath below. Assume that the IF stage of the first instruction is executed during cycle 1. Indicate the width and contents of the fD/EX pipeline register as it should be at the end of cycle 4. If the value cannot be determined, place a *?* in the entry. If the value is inconsequential, place an "X" in the entry. Since the multiplexors are not mapped to input selector values, assume that the topmost input is selected with value 0, the input below that is selected with value 1, etc