please correct this code

MSP430FR243x Demo - Configure MCLK for 1MHz operation, and REFO sourcing // FLLREF and ACLK. Use DCOFTRIM register to lock FLL. // // Description: Configure MCLK for 1MHz. FLL reference clock is REFO. // ACLK = default REFO ~32768Hz, SMCLK = MCLK = 1MHz. // Use DCOFTRIM register to lock FLL. If FLL is locked and // DCO tap is closest to 256, the DCOFTRIM value is the best one. // // MSP430FR2433 // --------------- // /|\| | // | | | // --|RST | // | | // | P1.0 |---> RED LED 7.63Hz 131 mSec // | P1.0 |---> GREEN LED 4 sec (2 on, 2 off) 0.25Hz // | P1.3 |---> MCLK = 1MHz // | P1.7 |---> SMCLK = 1MHz // | P2.2 |---> ACLK = 32768Hz // // Ling Zhu Texas Instruments Inc. // msp430fr243x_CS_02.c for reduced SMCLK Modified for Energia H. Watson 20180729 // sketch_CS_DCO_HW.ino //****************************************************************************** #include

void Software_Trim(); // Software Trim to get the best DCOFTRIM value

int main(void) { WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer

// SMCLK = MCLK/2 = 0.25MHz

__bis_SR_register(SCG0); // disable FLL CSCTL3 |= SELREF__REFOCLK; // Set REFOCLK as FLL reference source CSCTL0 = 0; // clear DCO and MOD FLL registers CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first CSCTL1 |= DCORSEL_3; // Set DCOCLK = 8MHz CSCTL2 = FLLD_1 + 121; // FLLD = 1, FFLN=121, DCODIV = 4MHz __delay_cycles(3); __bic_SR_register(SCG0); // enable FLL while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; // set ACLK = XT1 = 32768Hz, DCOCLK as MCLK and SMCLK source CSCTL5 |= DIVM1; // SMCLK = MCLK = DCODIV/4 = 1MHz,

P1DIR |= BIT0 | BIT1 | BIT3 | BIT7; // set P1.3 MCLK P1.7 SMCLK and P1.0 Red and P1.1 Green LED pin as output P1SEL1 |= BIT3 | BIT7; // set MCLK and SMCLK pin as second function P2DIR |= BIT2; // set ACLK pin as output P2SEL1 |= BIT2; // set ACLK pin as second function

PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on default high-impedance mode // to activate previously configured port settings // Configure Timer_A TA0CTL = TASSEL_1 | MC_2 | TACLR | TAIE; // ACLK, count mode, clear TAR, enable interrupt TA1CTL = TASSEL_2 | MC_2 | TACLR | TAIE; // SMCLK, count mode, clear TAR, enable interrupt

PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on default high-impedance mode //__bis_SR_register( GIE); //Enable interrupts __bis_SR_register(LPM0_bits | GIE); //Enable interrupts while(1);

}

// Timer0_A3 Interrupt Vector (TAIV) handler (ACLK/(2^16))*2 #pragma vector=TIMER0_A1_VECTOR __interrupt void TIMER0_A1_ISR(void) { switch(TA0IV) { case TA0IV_NONE: break; // No interrupt case TA0IV_TACCR1: break; // CCR1 not used case TA0IV_TACCR2: break; // CCR2 not used case TA0IV_TAIFG: P1OUT ^= BIT1; // overflow GREEN= 4 sec 0.25 Hz break; default: break; } }

// Timer1_A3 Interrupt Vector (TAIV) handler (SMCLK/(2^16))*2 #pragma vector=TIMER1_A1_VECTOR __interrupt void TIMER1_A1_ISR(void) { switch(TA1IV) { case TA1IV_NONE: break; // No interrupt case TA1IV_TACCR1: break; // CCR1 not used case TA1IV_TACCR2: break; // CCR2 not used case TA1IV_TAIFG: P1OUT ^= BIT0; // overflow RED= 131Msec 7.63Hz break; default: break; } }

the error says

exit status 1

invalid suffix MHz on integer constant