please create the circuit or draw the diagram

Submission file for this part: 6.circ Main circuit name: sequencecheck Input pin(s): inputx [1], sysclock [1] Output pin(s): outputr [1] Derive a minimal state table for a Mealy model FSM that acts as a sequence checker. During four consecutive clock cycles, a sequence of four values of the signal x is applied, forming a binary number. The oldest value of x would become the most significant bit in that binary number. The most recent value of x would become the least significant bit. The FSM will output outputr = 1 when it detects that the previous 4 bit sequence was either 0010 or 1100. At all other times, including when the previous sequence was not those described previously, outputr = 0. Implement the FSM as a circuit in Logisim Evolution. Note that much like the last problem, this is not a sliding window. After the fourth clock pulse, the circuit resets itself and is ready to take in the next 4 bit sequence. You may use a maximum of 3 flip flops for this problem. If you need to use more than 3 flip flops, your FSM is not minimized. You will lose a significant portion of credit if you have more than 3 flip flops in your circuit. You may use a maximum of 13 AND gates and 4 OR gates with any number of inputs. You will lose a significant portion of credit if you have more, as it means your combinational logic is not minimized. If you violate both this and the previous constraint, you will get a 0